Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit and a method for fabricating the same.
In general, packaging technology for semiconductor integrated circuits has been continuously developed to satisfy demands for miniaturization and mounting reliability. Recently, as the high performance of electrical and electronic products has been demanded with the miniaturization of electrical and electronic products, a variety of technologies for a stack package have been developed.
In the semiconductor industry, “stack” means vertically stacking two or more semiconductor chips or packages. When a stack package is applied to a semiconductor memory device, it is possible to realize a product having a memory capacity two or more times larger than a memory capacity which may be realized in a semiconductor integration process. Furthermore, the stack package not only increases the memory capacity, but also has an advantage in the packaging density and the use efficiency of mounting area. Therefore, the research and development for the stack package are being actively conducted.
The stack package may be fabricated by the following methods. First, individual semiconductor chips may be stacked, and then packaged together. Second, packaged individual semiconductor chips may be stacked. The individual semiconductor chips of the stacked semiconductor package are electrically coupled through metallic wires or through silicon vias (TSV). The stack package using TSVs has such a structure that the physical and electrical coupling between semiconductor chips is vertically achieved by TSVs formed in the respective semiconductor chips.
FIG. 1 is a diagram illustrating a TSV.
Referring to FIG. 1, a hole is formed through a semiconductor chip A, and a TSV B is formed by filling the hole with a metal. Then, a semiconductor chip C for stacking is prepared. A plurality of semiconductor chips C are stacked to form a semiconductor integrated circuit which is typically referred to as a 3D (three-dimensional) stack package semiconductor integrated circuit.
FIG. 2 is a perspective view of a 3D stack package semiconductor integrated circuit.
Referring to FIG. 2, the 3D stack package semiconductor integrated circuit (hereafter, referred to as “semiconductor integrated circuit”) 100 includes first to fourth semiconductor chips 110 to 140 and TSVs 150 to 170. The first to fourth semiconductor chips 110 to 140 are stacked vertically, and the TSVs 150 and 170 are formed through the second to fourth semiconductor chips 120 to 140, respectively, and configured to interface signals and power among the first to fourth semiconductor chips 110 to 140.
Among the first to fourth semiconductor chips 110 to 140, the first semiconductor chip 110 having no TSV is typically referred to as a master chip. The master chip is configured to buffer an external signal applied from outside, for example, from a controller and control the second to fourth semiconductor chips 120 to 140 through the TSVs 150 to 170. The second to fourth semiconductor chips 120 to 140 which are controlled by the master chip are typically referred to as slave chips.
FIG. 2 illustrates that each of the semiconductor chips includes only one TSV. In reality, however, the semiconductor chip may include at least several hundred to several thousand TSVs. The TSVs 150 to 170 serve to interface signals or power among the semiconductor chips 110 to 140. Accordingly, the TSVs 150 to 170 are formed of a metal having excellent conductivity, for example, Cu.
FIG. 3 is a plan view of the semiconductor integrated circuit 100 of FIG. 2.
In order to describe the configuration of the semiconductor integrated circuit 100, the fourth semiconductor chip 140 including a fuse circuit 180 will be taken as an example.
Referring to FIG. 3, the fourth semiconductor chip 140 includes an active area in which the fuse circuit 180 and other elements are provided and a non-active area in which the TSV 170 is provided. The non-active area may include a predetermined area surrounding the TSV 170 as well as the area in which the TSV 170 is provided. In such a non-active area, a variety of devices including the fuse circuit 180 are not formed, in order to prevent the degradation of the devices caused by the TSV 170. The non-active area includes dummy patterns for compensating level differences from various devices and metal interconnections formed in the active area. When the level differences are compensated by the dummy patterns, a pattern formation process of the TSV 170 may be easily performed.
When a fuse F1 is to be cut, the fuse circuit 180 inverts the logic level state of an output signal before the fuse is cut. Depending on whether or not the fuse F1 is cut, the fuse circuit 180 selectively outputs an option signal OUTPUT through an output terminal. The fuse F1 is a conductive pattern provided between two electrodes and is configured to electrically couple the two electrodes. The fuse F1 may be cut by an external process, such as by a laser.
The operation of the fuse circuit 180 is as follows. When a power-up signal PWRUP is activated, latch units LIN1 and LIN2 are initialized to determine the logic level state of the option signal OUTPUT of the output terminal. On the other hand, when the power-up signal PWRUP is deactivated, the option signal OUTPUT maintains the current state or is inverted and outputted, depending on the coupling state of the fuse F1. Such an option signal OUTPUT may be used for various purposes. For example, when the master chip 110 does not include a TSV and the slave chips 120 to 140 include the TSVs 150 to 170 as illustrated in FIG. 1, the option signal OUTPUT may be used as a signal for discriminating whether the corresponding semiconductor chip is the master chip 110 or the slave chip 120, 130, or 140, depending on the logic level state thereof. Meanwhile, a test mode signal TM is used for restoring the original state after the fuse F1 is cut.
The conventional semiconductor integrated circuit 100 configured in such a manner has the following problems.
As described above, the option signal OUTPUT outputted from the fuse circuit 180 may be used for discriminating the master chip and the slave chips. In order to indicate that a corresponding semiconductor chip is a slave chip, the process of cutting the fuse F1 should be performed. That is, a laser or the like is used to physically cut the fuse F1. As such, when the fuse F1 is to be cut, the fuse cutting process should be additionally performed. Therefore, a fabricating cost and time inevitably increases.